Elephantech Develops DeepVia™ Silicon: A High-Aspect-Ratio Seed Layer Solution for 3D Semiconductor Integration
― A Novel Approach for Silicon Via Seed Layer Formation Addressing Increasing Aspect Ratios ―

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Background

As AI accelerator performance continues to advance, the demand for higher density and smaller-diameter silicon vias in High Bandwidth Memory (HBM) and hybrid bonding is growing rapidly. Furthermore, as 3D integration architectures evolve—where multiple dies are vertically stacked—the required interconnect depth for silicon vias is increasing. With both diameter reduction and depth increase progressing simultaneously, via aspect ratios are rising at a pace exceeding previous technology generations.

Challenges of conventional processes

In forming copper seed layers for high-AR silicon vias, the dominant industry process, Physical Vapor Deposition (PVD/sputtering), faces fundamental physical constraints due to the “line-of-sight” nature of sputtered particles. This makes it difficult to achieve uniform coverage at the bottom and along deep sidewalls as aspect ratios increase. There is a growing need for a new approach that achieves both uniform coverage and mass production compatibility.

DeepVia™ Silicon Overview

Elephantech has developed a novel process for forming copper seed layers on the inner walls of high AR vias, combining proprietary 15 nm-class copper nanoparticles with inkjet printing equipment. Copper nanoparticle ink is dispensed into the vias by inkjet printing, where proprietary adsorption characteristics enable uniform coverage of copper nanoparticles across the entire inner via wall surface. Through drying and sintering, the nanoparticles coalesce to form a thin copper film, which serves as a seed layer for standard electrochemical copper plating (ECP) to complete the interconnection.

DeepVia™ Silicon Process

Core Technology and Advantages

1. Distinctive Adsorption Behavior of Copper Nanoparticles

In typical nanoparticle deposition, particles often agglomerate into “islands”, making it difficult to form a continuous film. This island formation is a common challenge in thin film growth processes and is a factor that inhibits the formation of a continuous conductive path.
Elephantech’s 15 nm-class copper nanoparticles are engineered to self-assemble and adsorb densely onto the barrier layer (such as Titanium) without agglomeration. This characteristic enables the formation of a uniform, continuous seed layer.

Outlook

Elephantech is currently conducting collaborative evaluations of this technology with memory manufacturers, foundries, and advanced packaging companies. Following verification of copper nanoparticle adsorption and plating connectivity on Ti (titanium) barrier layers, detailed evaluation is underway toward application to actual silicon vias, and Elephantech will accelerate the deployment of solutions addressing challenges in AI semiconductors. In addition to the currently demonstrated Ti (titanium) barrier layer, verification of applicability to other barrier metals including TiN is being pursued in parallel with customer evaluations.
For inquiries regarding evaluation and sample provision, please contact us at the address below.